In video system applications, a video stream may need to be processed when it is received and before it is transmitted, displayed, and/or stored. For example, when a video stream is to be transmitted and/or stored, the video fields and/or frames that comprise the video stream may be compressed to reduce redundant information and increase the amount of video content that may be transmitted in a transmission channel and/or the amount of video content that may be stored in a storage device. A video frame may refer to a picture in the video stream while a video field may refer to one of two separate sub-pictures that may be formed from a video frame. In this case, one or more video encoders may be utilized to compress the video stream in accordance with the specifications and requirements of the transmission channel and/or the storage device. The encoded video fields and/or frames in an encoded video stream may be decompressed to reproduce the original video content in the video stream. In this case, video decoders may be utilized to decompress the encoded video stream.
In another example, when a video stream is to be displayed, the video stream may be modified or adapted to a particular format in order to conform to a particular display device. This may occur in instances when, for example, interlaced video format is to be displayed on a display device that supports progressive or non-interlaced video format. In interlaced video, the display device may support the use of video fields, while in progressive, or non-interlaced, video the display device may support the use video frames. When the video stream comprises video fields and the display device only supports progressive video, a deinterlacer may be utilized to convert the video stream into a stream of video frames that may be displayed by the display device.
The design and implementation of video processing systems, such as encoders, decoders, or deinterlacers in integrated circuits (ICs) may be very complex since many different subsystems are necessary to perform and/or control the operations that compress, decompress, and convert interlaced video into progressive video. As a result, the operation and/or functionality of the many different subsystems that comprise these complex architectures may be very difficult to verify during the design phase. Moreover, the operation and/or functionality of video processors may dynamically change since the contents of a video stream may be changing with time. This difficulty persists whether benchtests generated for verification are developed for video processor hardware models based on a Register Transfer Level (RTL) description or on representations based on hardware description languages (HDLs). For example, hundreds or even thousands of video fields and/or frames may be necessary to verify a portion of the operations in a specific hardware implementation of a video processor. In this regard, finding and isolating design flaws may be very time consuming and may lead to either an incomplete verification of a video processing system or to a prolonged verification period which may adversely affect the time-to-market of a product.
It may be quite common that a video processor design would have separate control data flow and video data flow paths. It may also be quite common that the amount of control data flow and video data flow varies significantly, i.e., the data flow is such that a digital video system is unbalanced. To test and verify these two types of blocks while operating together may usually require very long simulation times. Moreover, it may still be likely, even after a long simulation, that the operation of these types of blocks may be severely under tested. The situation may be even worse when the two types of blocks have data dependency from each other such as a feedback loop control.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.